Phase lock loop (PLL) technology has proven to be extremely useful in analog electronic circuits and its application to digital circuits is attractive and growing. In a copending application Ser. No. 550,526 filed Nov. 9, 1983. A DIGITAL PLL DECODER is described in connection with a communications system. The application, which is assigned to the assignee of the present invention, is incorporated herein by reference. A multiphase clock source develops a plurality of clock signals which have phase-offset characteristics. When a comparison of the receiver clock with the received clock signal shows an offset, the clock phase is changed to another clock phase to minimize the offset. Thus, the receiver clock is effectively synchronized with the received signal (transmitter) clock. By performing the locking with digital signals the receiver does not require precision external components. This system is effective in receiver clock locking and it is fully capable of phase locking to the accuracy required in most communications systems it operates. It would be helpful to incorporate a vernier phase shifter for the clock pulses to increase the phase lock accuracy.